Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms
Best Paper Nominee
Qijing Huang, Po-An Tsai, Joel S Emer, Angshuman Parashar
International Symposium on Computer Architecture (ISCA), 2024.
DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators
Charles Hong, Qijing Huang, Grace Dinh, Mahesh Subedar, Yakun Sophia Shao
International Symposium on Microarchitecture (MICRO), 2023.
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design
Qijing Huang, Charles Hong, John Wawrzynek, Mahesh Subedar, Yakun Sophia Shao
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2022.
Adaptive Test Generation for Fast Functional Coverage Closure
Azade Nazi, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhosseini, Richard Ho
Design Verification Conference (DVCON), 2022.
Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage
Qijing Huang, Hamid Shojaei, Fred Zyda, Azade Nazi, Shobha Vasudevan, Sat Chatterjee, Richard Ho
Design Verification Conference (DVCON), 2022.
HAWQ-V3: Dyadic Neural Network Quantization
Zhewei Yao, Zhen Dong, Zhangcheng Zheng, Amir Gholami, Jiali Yu, Eric Tan, Leyuan Wang, Qijing Huang, Yida Wang, Michael W. Mahoney, Kurt Keutzer
International Conference on Machine Learning (ICML), 2021.
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators
Qijing Huang, Minwoo Kang, Grace Dinh, Thomas Norell, Aravind Kalaiah, James Demmel, John Wawrzynek, Yakun Sophia Shao
International Symposium on Computer Architecture (ISCA), 2021.
HAO: Hardware-Aware Neural Architecture Optimization for Efficient Inference
Zhen Dong*, Yizhao Gao*, Qijing Huang, John Wawrzynek, Hayden So, Kurt Keutzer
Field-Programmable Custom Computing Machines (FCCM), 2021.
CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on FPGAs
Qijing Huang*, Dequan Wang*, Zhen Dong*, Yizhao Gao, Yaohui Cai, Tian Li, Bichen Wu, Kurt Keutzer, John Wawrzynek
International Symposium on Field-Programmable Gate Arrays (FPGA), 2021.
BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors
Farzad Farshchi, Qijing Huang, Heechul Yun
Real-Time and Embedded Technology and Applications Symposium (RTAS), 2020.
AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs
Keertana Settaluri, Ameer Haj-Ali, Qijing Huang, Kourosh Hakhamaneshi, Borivoje Nikolic
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020.
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning
Ameer Haj-Ali*, Qijing Huang*, William Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek
Proceedings of Machine Learning and Systems 2 (MLSys), 2020.
Algorithm-hardware Co-design for Deformable Convolution
Qijing Huang*, Dequan Wang*, Yizhao Gao, Yaohui Cai, Zhen Dong, Bichen Wu, Kurt Keutzer, John Wawrzynek
5th Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications (EMC2), 2019.
Centrifuge: Evaluating Full-system HLS-generated Heterogeneous-accelerator SoCs using FPGA-Acceleration
Qijing Huang, Christopher Yarp, Sagar Karandikar, Nathan Pemberton, Benjamin Brock, Liang Ma, Guohao Dai, Robert Quitt, Krste Asanovic, John Wawrzynek
International Conference on Computer-Aided Design (ICCAD), 2019.
AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning
Qijing Huang*, Ameer Haj-Ali*, William Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek
International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2019.
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees Vissers, John Wawrzynek, Kurt Keutzer
International Symposium on Field-Programmable Gate Arrays (FPGA), 2019.
Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim
Farzad Farshchi, Qijing Huang, Heechul Yun
2nd Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications (EMC2), 2019.
FPGA Accelerated INDEL Realignment in the Cloud
Lisa Wu, David Bruns-Smith, Frank A Nothaft, Qijing Huang, Sagar Karandikar, Johnny Le, Andrew Lin, Howard Mao, Brendan Sweeney, Krste Asanović, David A Patterson, Anthony D Joseph
International Symposium on High Performance Computer Architecture (HPCA), 2019.
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
IEEE MICRO Top Picks from Computer Architecture Conferences
Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, Krste Asanovic
International Symposium on Computer Architecture (ISCA), 2018.
Synthesis of Program Binaries into FPGA Accelerators with Runtime Dependence Validation
Best Paper Award
Shaoyi Cheng, Qijing Huang, John Wawrzynek
International Conference on Field Programmable Technology (FPT), 2017 .
The Effect of Compiler Optimizations on High-level Synthesis-generated Hardware
Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Nazanin Calagar, Stephen Brown, Jason Anderson
ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2015.
From Software to Accelerators with LegUp High-level Synthesis
Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz Czajkowski, Stephen Brown, Jason Anderson
International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2013.
The Effect of Compiler Optimizations on High-level Synthesis for FPGAs
Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Stephen Brown, Jason Anderson
International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2013.